Hi, when I used netgen tool for LVS, it can work for flatten netlists. However, it can not work for hierarchical netlists, as shown . How I can fix it?, can you give me some tips?. I hope my question is clear
a
Arman Avetisyan
08/20/2022, 2:55 PM
how it supposed to know which cells to compare. The arguments need to look like: nelist_name subckt_name
✅ 1
Arman Avetisyan
08/20/2022, 2:55 PM
e.g. netlist.spice inv_1 netlist_2 inv_1
✅ 1
Arman Avetisyan
08/20/2022, 2:56 PM
The flatten netlist should not be used because its missing pins, therefore pin checks
✅ 1
t
Tim Edwards
08/20/2022, 5:08 PM
@Ahmed Reda: For the hierarchical case, use the syntax
. If you just provide a file name, then netgen sees subcircuits but does not see those subcircuits instantiated anywhere, and so its understanding is that it is looking at a library of subcircuit components and not a netlist. You have to tell it what subcircuit is to be considered the top level of the design.
Linen is a search-engine friendly community platform. We offer integrations with existing Slack/Discord communities and make those conversations Google-searchable.