Hello, I'm working on using SKY130 for a top chip design. I tried to used sky130_fd_io__top_gpiov2 macros for the signaling. I tried to connect the signal at the RTL level, but somehow, the signal isn't able to go into the core (both normal signal and clock signal). Was there something wrong with my configurations?

@Thanh Vũ I haven’t done verilog simulation on the io cells (or anywhere else for that matter), but from the

caravel/rtl/pads.v

file

sky130_ef_io__gpiov2_pad_wrapped X``_pad ( \
        `MGMT_ABUTMENT_PINS \
        `ifndef TOP_ROUTING \
                .PAD(X), \
        `endif  \
                .OUT(Y_OUT),    \
                .OE_N(OUT_EN_N), \
                .HLD_H_N(loop_one_``X), \
                .ENABLE_H(porb_h), \
                .ENABLE_INP_H(loop_zero_``X), \
                .ENABLE_VDDA_H(porb_h), \
                .ENABLE_VSWITCH_H(loop_zero_``X), \
                .ENABLE_VDDIO(CONB_ONE), \
                .INP_DIS(INPUT_DIS), \
                .IB_MODE_SEL(CONB_ZERO), \
                .VTRIP_SEL(CONB_ZERO), \
                .SLOW(CONB_ZERO),       \
                .HLD_OVR(CONB_ZERO), \
                .ANALOG_EN(CONB_ZERO), \
                .ANALOG_SEL(CONB_ZERO), \
                .ANALOG_POL(CONB_ZERO), \
                .DM(MODE), \
                .PAD_A_NOESD_H(), \
                .PAD_A_ESD_0_H(), \
                .PAD_A_ESD_1_H(), \
                .IN(Y),  \
                .IN_H(), \
                .TIE_HI_ESD(loop_one_``X), \
                .TIE_LO_ESD(loop_zero_``X) )

sky130_ef_io__gpiov2_pad_wrapped

is a wrapper for the io cell you’re using. The wrapper definition is in

$PDK_ROOT/$PDK/libs.ref/sky130_fd_io/verilog/sky130_ef_io.v

but it looks to be a direct mapping. So in answer to your question, I imagine that the circuit won’t work unless all the

ENABLE

signals have the correct levels. Don’t know if it will make much difference, but the external input is actually connected to the

PAD

port. The

PAD_A_ESD_0_H

signal is an internal connection to the

PAD

through a small resistor.

Tsk for the reply, i'm trying to implement a physical design using this macro. I was wondering, what is the loop_one/zero_''X mean in for the macro?

The code snippet above is part of a macro definition for

INOUT_PAD

. ```X` refers to the first parameter of the macro, I think. It creates a unique connection from the outputs

TIE_HI_ESD

and

TIE_LO_ESD

of each io cell back to the inputs of that io cell.