Hi, I did LVS on my complete design. I get everything matched except my substrate are all floating although I had assigned labels to both bulks of nmos and pmos. The nmos is extracted with VSUBS as the bulk terminal. Does anyone know how to connect the bulk terminals?

@Utkarsh Sharma Can you share your lvs results?

Please find gds and extracted file attached.

@Utkarsh Sharma There is no text on either of the hierarchies extracted. I suggest that you add ports.

When you read the gds using magic, don't you see GND label on the guard ring around the mosfets?

The ports are not at the top level. They are inside subcells that are not hierarchically extracted

I see. But the port connected to bulk isn't identified inside the subcells? It is always VSUB?

If the bulk connection is unlabeled, I believe it defaults to

VSUB

.