Hi everyone. Is thermal aware floorplan and placement is something that should be considered in a 2D ic design?

Reliability and design engineer here. Joule heating is a thing for advanced nodes, and depending on design (example: RF power amplifier dissipate a lot of power). For older nodes like sky130 and those available as OpenPDK, the thermal aspect is usually well enough covered by the high temperature in PVT corners. Say you use SS/FF, VDD±10%, and -40°C and 125°C. 125°C is the maximum junction temperature (SPICE simulation temperature retrieves corresponding transistor characteristics in the model card) and secure your timings and leakage, not the ambiant temperature: if ambiant temperature is 85°C you have 40°C headroom for joule heating, more than enough for most applications. Then it's a matter of system design: radiator or fan on the chip, package thermal conduction, etc… It could help to have some on-chip temperature measurement using some junction. Additionally, industry standard technology qualification covers 125°C junction temperature for nominal voltage +10%. Overdrive and overclocking like CPUs requires a bit more care, hard breakdown risk could be budgeted according to overall involved gate oxide area, end of life functional reliability proven by HTOL test on actual chips in package.

@Germain B thanks for the input .

How much power dissipation do you expect from this complex digital design?

Sorry i don't have any particular design configuration in mind, I am trying to understand the relevance of this approach.

I would say only relevant for power hungry digital design, like state-of-the-art advanced CMOS CPU and GPU. Those 3 questions are fundamental, and the common approach in case the heating is too much is to monitor on-chip temperature and reduce workload at system level and/or increase fan speed to keep temperature under control. In my opinion distributing power consumption over the chip could only help marginally… If junction temperature is never trepassing 125°C for consumer application is fine (usually specs 10years 125°C 1000 ppm failure rate Vnom+10% very large gate oxide area).

okay got it