#265 Layout efficiency: Substrate tap, nwell tap, vias, improved MOSFET cells Issue created by hpretl Maybe I just don't know how to do it properly, but it looks like a few fundamental thing are still missing from the KLayout setup: • Via generator (with selectable start and end layers, and number of X/Y multiples) • Substrate contact (maybe merge into via generator); ideal would be the possibility to make a substrate contact as a path • Option to NMOS pcell to add a guardings • Nwell contact (maybe merge into via generator); ideal would be the possibility to make an nwell contact as a path • Option to PMOS pcell to add a guardings In addition, it would be good have the option in the MOSFET pcells to have the gates connected. IHP-GmbH/IHP-Open-PDK