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Has any group been able to do LVS and PEX properly? I'll like to discuss about it.
# ieee-sscs-dc-24
s
Has any group been able to do LVS and PEX properly? I'll like to discuss about it.
m
What are the issues you are seeing. I think it would be goodd to try it on something you know is clean to have a better understanding
s
Sorry for late reply. About LVS , nothing seems to work for me. here are my code block and the LVS errors. Is there any documentation about how to do LVS step by step?
fvf.pyLVS
m
can you provide the gds and schemtics used for this LVS. It is easier to debug/reproduce.
s
I am not able to do LVS using the schmatic. It shows this error-"FileNotFoundError: [Errno 2] No such file or directory: '/tmp/tmpap1jbqee/fvf_lvs.rpt'"
fvf.gdsfvf.sch
I am really new to these things, let me know if I am doing something wrong. thanks
I think I probably understand one of the errors at least. You see, for our case, the two pwells are sperated by dnwell. We give different bias to thsese pwells. I think it does not identify that, and converts all the dummies into one parallel device, thus creating total three instances of nfet. Also I am getting an VBULK not connected error
fvf.gds
fvf.gds
While doing DRC, I got a warning saying can not identify layer 64:44 which is the pwell....idk if that is the reason for lvs fail also
m
@Mitch Bailey Any thoughts?
m
I’ll look into it and reply later.
s
I did LVS for the case when source and bulk of the input fet is not shorted and it passed the LVS
with this current format lvs passes for 1. device type pmos and sb_short=true 2. device type nmos and sb_short=False. When shorting the S and B for both devices inside the dnwell for nmos, for GDS netlst it keeps merging all the dummies as one device
fvf.py
m
In the sky130 process, there is no 
pwell
mask layer. Every thing that is not 
nwell
is 
pwell
. So the 
pwell
drawing layer that in your design has no effect and 
VOUT
and 
VBULK
are shorted through 
pwell
. Also, please be aware that for the sky130 process, deep nwell must be surrounded by an nwell guard ring, connected to n-diffusion. The voltage level should be greater than the enclosed pwell to avoid forward biasing. In the attached diagram, the red and blue nets are shorted through pwell. To actually realize to separate pwells of different potentials, surround each area with an nwell ring.
s
understood, thanks a lot
πŸ‘ 1
I changed my design accordingly and now it is LVS clean
πŸ‘ 1
Hi @Mitch Bailey, I have two doubts about LVS. I was trying to do LVS of our final block against spice netlist. I keep getting two errors.
1. device mismatch for pfet lvt. I would like to know how lvs handles dummies for pmoses and nmoses. It looked like for NMOSES it merged all the dummies irrespective of there W and L. However for pmoses, If that is not the case, would perfectly explain the error I am getting.
2. Disconnected node VSS. I tried many time by moving the VSS pin directly above well ties. I keep getting the same error
m
Can you share your netlists and LVS results?
s
I tried by changing the number of dummies in the spice file, I could not get it to work.
ota.pyotalvsota.spice
m
Looks like there a VCC - VSS short in the layout. Can you share your latest layout (gds)?
s
Here it is
ota.gds
m
@Subham Pal the nwells on the left and right are missing ntap. They are surrounded by ptaps that short VCC to VSS through the substrate. See screenshot. Also, for sky130 process, the pwell layer is unused. If you want isolated pwell, you need to use deep nwell and surround that with an nwell ring. The area inside the deep nwell that is not nwell will be pwell.
s
Oh thank you very much, all this time I was thinking that as of a ntap, and at first our goal was to use dnwell and we already made this layout having that on mind. However, even without dnwell the circuits shows good performance, so we decided to remove it and keep the structure.
πŸ‘ 1
The current mirror Pcell adds a ptap as welltie and adds a pwell irrespective of the device type. this leads to those LVS errors.
m
I think the nwell should be bigger and the tap be changed from ptap to ntap. Do you know who is responsible for the 
current_mirror
?
s
I do not know that, I will try to modify this code some time after. I think our OTA will pass LVS after this change.
s
I actually am facing the same errors in LVS trying to just do a simple current mirror (project goal : regulated CM). I have pushed some changes to CM which decrease the erros. My PR is still waiting review from maintainers. I will post my LVS and GDS here, in a seperate chat. Seems I can get more help here.
πŸ‘ 2
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