This is Yuta Shiomi from the SaltyChip team.
During yesterday's Chipathon meeting, I struggled to effectively discuss the implementation of the MIM capacitor due to my limited English skills. Therefore, I’d like to take this opportunity to revisit the topic here.
First, the reason I built the MIM capacitor array from scratch was that I needed to design a layout specifically tailored for a 6-bit SAR ADC.
Since this is my first time working on integrated circuit design, I wasn't very familiar with layout methodologies. To guide me, I referred to the following paper:
"High-density MOM capacitor array with novel mortise-tenon structure for low-power SAR ADC"
https://ieeexplore.ieee.org/document/7927277
I attempted to create a layout similar to the one shown in Fig. 6 (the attached figure) of this paper, including the placement of vias and dummy metal. However, I couldn’t figure out how to express this layout effectively using the MIM capacitor array function provided by OpenFASOC, so I ended up building it from scratch.
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[Proposal]
The MIM capacitor array function provided by OpenFASOC currently allows you to specify only the size, number of rows, and number of columns for the MIM capacitors. Additionally, the generated array connects all the MIM capacitors with metal by default.
Considering my need for a more flexible MIM capacitor array, I believe it would be beneficial to extend the functionality of this tool. Specifically, it would be helpful if the metal connections and via placement within the MIM capacitor array could be configured based on their positions in the grid.
If this proposal aligns with the goals of the project, I would greatly appreciate it if you could consider it. Thank you.