How do you make connection of a mos device with fingers more than one? I have a circuit with large width, so I used nf to do the layout. But I am having difficulties with connections, like I can't understand the source and drain connections that I have to do. For clarity I have uploaded the .mag and the .sch for the circuit.

@Jazim Ibrahim unfortunately, only sharing the top level of a hierarchical magic database doesn’t provide much clarity. If your using a device generator to create the individual mosfets, there’s a parameter for the number of fingers. Connect every other diffusion as the source and the remaining as the drain.

@Mitch Bailey Thanks for the response. I have inductors in my design, and I've used an square inductor generator tool to generate the mag of inductor. Now I'm trying to use the inductor test coils in the device generator. How can you caclculate the inductance of the generated coils?

I have no experience with calculating the inductance of coils. You might need to do some tricks if you want to extract them. I’ve seen designs where the inductors are placed in standalone cells and those cells are abstracted to create inductors that can be used in LVS (schematic side is also a black box). You might need to add a metal resistor to prevent the inductor terminals from shorting.

I am still new to all these tools , so how do you go about doing that or are there any materials you could share which I could refer?

If you are not using the precheck LVS system, the in magic these are the commands to cause a cell to be abstracted.

load <inductor_cell>
property LEFview true

For precheck, just add the cell name to the

EXTRACT_ABSTRACT

cell list. Match the cellname to the schematic device name which should be netlisted as a primitive device. (Set

type=primitive

on the schematic symbol). To prevent the ports from shorting, add a

rmetal*

resistor to the layout.

Do I have to load the inductor in a separate magic window , add the property, then save it and add that inductor as an instance in the magic terminal in which I import the spice of my circuit?

@Jazoolee Ahamed That sounds right, although I have never actually done it myself.

Who should I ask to know more about this?

Maybe ask on the channel of the process you are using.

I asked there previously and didn't get much help. I asked in the magic channel.

Sorry, I don’t know anything other than using the device generator.

I also used the device generator. If I don't use mf value then there is a capacitor area violation.

@Jazim Ibrahim can you share a screen shot? I’m not exactly sure what you’re asking. Do you want to know how to create a mim capacitor with a specific mf value or how to connect it? Connecting is just wiring to the terminals, I think.

So like in my design i am using comparatively large fet's. So here if I generate the spice, it will show something like .subckt sky130_fd_pr__nfet_01v8_9SJUWP a_n275_n1174# a_n33_1022# a_15_n1000# a_n173_n1000# + a_63_n1088# a_111_n1000# a_n81_n1000# a_n129_n1088# X0 a_111_n1000# a_63_n1088# a_15_n1000# a_n275_n1174# sky130_fd_pr__nfet_01v8 ad=3.1 pd=20.62 as=1.65 ps=10.33 w=10 l=0.15 X1 a_n81_n1000# a_n129_n1088# a_n173_n1000# a_n275_n1174# sky130_fd_pr__nfet_01v8 ad=1.65 pd=10.33 as=3.1 ps=20.62 w=10 l=0.15 X2 a_15_n1000# a_n33_1022# a_n81_n1000# a_n275_n1174# sky130_fd_pr__nfet_01v8 ad=1.65 pd=10.33 as=1.65 ps=10.33 w=10 l=0.15 .ends So for testing the connection (mainly to learn), I designed a simple circuit with a resistor and a transistor (with nf=3, w=30 l=0.15). I attached the spice of the circuit, the schematic, the mag and the spice extracted from the mag. I want to know when I use nf value transistor, it will show a single transistor with fingers, should I connect in between the transistor fingers for that to be taken as a single device? If not how should I go about doing the connections?

Normal magic extraction will not merge the fingers. Each device will be extracted separately.

Yes but in the lvs it was showing something like merging parallel devices and ultimately showed 1 device even though I used fingers. I will attach the lvs comp.out file.

Right, netgen will flattened unmatched hierarchies

Flattening unmatched subcell sky130_fd_pr__nfet_01v8_P259ST in circuit justatest (0)(1 instance)

and reduce parallel devices

sky130_fd_pr__nfet_01v8 (24->1)            |sky130_fd_pr__nfet_01v8 (1)

Should I read in the layout and generate the extracted netlist using klayout?

I have never (well almost never) extracted the layout with klayout. I almost exclusively use the precheck lvs. Create an

lvs/cellname/lvs_config.json

file

make precheck
make lvs-<cellname>

After this what should I do?

That is all you need to do to run LVS on a gds file. You’ll need to add the appropriate settings to

lvs_config.json

. See here. Let me know if you have problems.