Hi everyone, I'm trying to create a layout from an xschem schematic, but I'm facing some issues. Here's what I’ve done so far: Created an inverter schematic in xschem and generated the netlist by selecting LVS netlist: Top level is a .subckt from simulation -> LVS window. Imported the devices from the SPICE file (generated by xschem) into Magic and connected them with metal 1. Used these commands to generate the SPICE file from the layout: save file_name.mag extract all ext2sim ext2spice Ran netgen for LVS using: lvs xschem_spice.spice magic_file.spice sky130_setup.tcl However, the netlists are not matching. Can someone guide me where I might be going wrong? Or if you have a tutorial that goes through xschem to Magic and then comparing with LVS, that would be helpful. Thanks in advance!

@Pathan Rehman Ahmed khan-student 1. Sharing your LVS output would help. (you just shared - thanks). 2. Although either direction is ok, the general consensus is that in LVS (layout vs schematic), the layout is specified first. There’s no way to tell from the report file, so using this convention makes it easier on everyone.

netgen -batch lvs "magic_file.spice cellname" "xschem_file.spice cellname" sky130_setup.tcl

3. For LVS, you probably don’t want

ext2sim

but probably should use

ext2spice lvs

before

ext2spice

. 4. Looks like the mag file is missing ports. Check the documentation on how to create ports (not just text). Without ports, the top layout is not extracted as a subckt.

4. Actually, I have imported the spice file from the xschem, it already gave me the ports with it? Is that not actual ports?

Sorry, don’t know about that. Looks like the extracted spice file is not recognizing ports. Check out http://opencircuitdesign.com/magic/commandref/port.html

@Pathan Rehman Ahmed khan-student: The issue is in the way you do extraction from magic. Make sure you do

ext2spice lvs

before you do

ext2spice

. Without doing that, you lose the hierarchy, the subcircuit wrapper, and you get an output that is SPICE-3 compatible, not ngspice compatible. You did not need to do

ext2sim

, which has no bearing on LVS.

@Tim Edwards, sir, these are my SPICE files from Xschem and Magic. Should the SPICE files look this way, or am I making a mistake in the process? I have also attached a snapshot of my comp.out and the layout. I am a beginner with the layout, so please excuse my mistakes. Thank you!

The extract netlist is correct. The netlist generated from xschem is not. Be sure to chose

Simulation

>

LVS

>

LVS netlist: top level is a .subckt

before generating the netlist.

am i doing anything wrong in ports?

@Pathan Rehman Ahmed khan-student The ports look good to me. Your layout does not have a well or substrate connection, so it won’t pass LVS. You’ll probably want to add an nwell tap to VDD and a substrate tap to VSS.

this time, i have added nwll and substrate tap to VDD and VSS and the following results are attached in the screenshots

@Pathan Rehman Ahmed khan-student The schematic generated netlist looks good. The extracted netlist, however, is missing the bulk connections.

.subckt inversor A VDD Q VSS
X0 Q A VSS a_754_n1038# sky130_fd_pr__nfet_01v8 ad=0.29 pd=2.58 as=0.29 ps=2.58 w=1 l=0.15
X1 Q A VDD w_708_114# sky130_fd_pr__pfet_01v8 ad=0.29 pd=2.58 as=0.29 ps=2.58 w=1 l=0.15
.ends

a_754_n1038#

should be

VSS

and

w_708_114#

should be

VDD

. Looks like the layout is missing

viali

between the

metal1

and

locali

@Mitch Bailey thanks for the reply, yes indeed I was missing a bulk connection, but I have connected metal1 and locali with mcon and still LVS has matched..

@Pathan Rehman Ahmed khan-student If you share your lvs results, I might be able to help.

comp.out

Looks like it passes to me

Final result: Circuits match uniquely.

What problems are you seeing?

no, sir.. the inverter LVS has passed.. thanks for your help.. But, I am encountering another problem for opamp layout.. how to declare nets in layout?

You don’t need to. If the netlists are topologically equivalent, the internal node names are irrelevant. The layout does not match the schematic. For example, M1 and M2 in the schematic have a source and bulk connection to net3 which is output on M5, a pfet with the gate tied low. The layout pfet with the gate tied low is X3, but it’s output

a_1034_1715#

is not connected to anything that I can see. It is definitely not connected to the bulk of X8 and X10 which correspond to M1 and M2 in the schematic. The M2 pfet with vin_p connected to the gate has net2 as output in the schematic, but the corresponding X8 in the layout has the output shorted to VGND.