1) Is there any documentation about the various wishbone pins and their functionalities? 2) What is the purpose of the la_oenb pins, are they used for configuring the la i/o pins or something else? 3) What does fp_core_util and pl_density do?

(1) Wishbone is an open-source specification, so information about the interface can be found online. I find it easiest to work by example, though. (2) The

la_oenb

pins can be treated as 128 additional signals from the management processor to the user project area. They were originally intended to be used in the user project to multiplex signals between the logic analyzer and an external source. However, since that functionality is entirely up to the user to implement, in effect the signals can be used for anything. (3) That's a question for #C016H8WJMBR . The variables affect the ratio of logic cells vs. padding for a fixed layout area.