<@U03B029DKU5> I would like to share with you the ...
# chilechipmakers
k
@aquiles viza I would like to share with you the script with parse the verilog module inputs/outputs in order to generate xschem symbols for the purpose of mixed signal co-simulation. The script right now sources a hard coded file name what should be changed (the file name should be passed as a script parameter). I guess that generating a symbol where the symbol name is the same as module name is a good idea.