How does one decide how many power pins / pad are needed when designing a pad frame ?

Each pad is usually rated for a certain mA of current. You should have enough pads to supply the peak required mA of the design, plus a little bit extra for safety. If you have the resources, you can do power simulations with pads to ensure that the IR drop is adequate.

Unfortunately I don't see any such thing in the iHP PDK ...

Then I would either ask the PDK developers, or just throw on as many pads as possible and hope for the best 🤷‍♂️ If they tell you the size of the bondpads / bumps you might be able to make an estimate. I think most pads are somewhere between 100-400 mA but don't quote me on that.

If you have a dedicated I/O port you probably want at least one power/ground pair in the port. Most chips have VDDIO/VGNDIO separate from internal. Also, the bond wires and leadframe fingers have RLC. More allows you to put that in parallel.

ATM I have 2 pair (2xGND/ 2xVDD) for core voltage, and 3 pairs for IO voltage.

Sylvain, A few approaches: 1. Base functionality don't care about SSO, Ground noise or IO speed: 1 pwr, 1 gnd for each power domain you want. 2. Care about speed but not jitter or small timing effects on the IO that are second order to my oeprating frequency. ( You can probably get away with 1 pwr pad and 1 ground pad for every 16 IO cells. 3. If you care about SSO and second order noise and jitter you will want AT LEAST one pwr and one ground for evey 8 pads and you want them distributed so that it is PWR, 4 pads, GND 4 pads, PWR ...and so on. THis minimized CUM IR drop to the worst pad and gets timing close to optimimum with a reaosnable number of pads. 4. If you need to meet a DC current spec you must have at least enough pads to cover that current. THis can be detmerined from bond wire current carrying capacity on the PWR and ground pads. Divided by max IOH or IOL per pad gives you the number of ads each ground or pwr can support. 5. If you are desinging a differential high speed phy you want one pwr and one ground for each pair of signal wires and you place them on opposite sides of the phy. You route both power and ground to the cetner of the phy pair and tap off at thay oint to the drivers for the 2 IO cells. THis means both channels will see identical IR drop at all times.. Hope this helps.

Yes, thank you.