I have a test bench which uses `d_cosim` block which is a simple decoder with registered output. Th...

Krzysztof Herman

09/27/2024, 12:43 PM

I have a test bench which uses

d_cosim

block which is a simple decoder with registered output. The verilog module was evaluated using

iverilog

and

verilator

test benches and works as expected. Unfortunately I can not reproduce the same behavior during the simulation using ngspice. The module does not follow the truth table defined in the decoder. The question is how can I debug it using ngspice ?

Krzysztof Herman

09/27/2024, 12:56 PM

The decoder module is defined as follows:

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module decoder(
    input clk,
    input rst,
    input [3:0]  ctrl,
    output [7:0] dout_p,
    output [7:0] dout_n
  );

I found a difference in module behavior (ngspice) when I change the definition to

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module decoder(
    input clk,
    input rst,
    input ctrl_1,
    input ctrl_2,
    input ctrl_3,
    input ctrl_4,
    output [7:0] dout_p,
    output [7:0] dout_n
  );

however still it is not what is to be correct. The spice level code which defines the module is the following:

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adut [ net8 net22 net9 net10 net12 net13 ] [ net1 net2 net3 net11 net4 net5 net6 net7 net15 net14 net16 net17 net21 net18 net19 net20 ] null dut
.model dut d_cosim simulation=./decoder.so

where the respective net names correspond to to the inputs and outputs of the module ie.

net8 -> clk, net22->rst

Holger Vogt

09/28/2024, 10:04 PM

Krzystof, may I suggest that you post this question in the ngspice discussion forums? That will probably be the best way to meet the specialists. Holger

Holger Vogt

10/01/2024, 2:51 PM

You may be a victim of https://sourceforge.net/p/ngspice/bugs/686/ . Has been corrected in git branch pre-master-44.

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