When we include our module inside the user_proj_example and initialize it without connecting any of the IO ports, it should still synthesize when we run "make user_proj_example" right?

I'm pretty sure that command will use the pre-hardened user project design, so it won't synthesize it. It will just connect the wires. I'm not sure what would happen if there are no wires connected, maybe the whole module would get optimised out

So if i want to integrate my module with caravel, how should i go about it? Can you provide any references please

make user_proj_example

will harden your macro and integrate with

make user_project_wrapper

If the clock pin is not connected yosys may optimize your design to nothing.

even with the clock and reset pins connected it is still not synthesizing fully