<!channel>: Chipalooza update: The 2nd test chip with Chipalooza projects went out with the September shuttle run. Although it's called the Chipalooza test chip, it's a combination of circuits from Chipalooza and a number of circuits that I whipped up on short notice to fill in the gaps, or pulled from past open MPW runs. I used the same structure as I used for the first test chip, which divided up the user project area into fourteen areas individually powered through massive pFET switches (designed a long time ago for an early ChipIgnite run by Weston Braun at Stanford). The projects on the chip are as follows: 1. Programmable PLL from Hafiz Azeem Abbas and team 2. CMOS voltage reference by Adan Kvitschal 3. LDO by Alexandre Menu 4. Ultra-low-power comparator by Jun Yan Lee and team 5. Audio DAC driver by Harald Pretl's group at JKU 6. Stephen Wu's bandgap-referenced POR 7. Current bias generator (mine) (this delivers current biases to other projects and is not power-switched). 8. 8-bit IDAC (mine, based on the current bias generator) 9. 12-bit CDAC (mine) 10. 16 MHz R-C oscillator (mine) 11. 500 kHz R-C oscillator (mine) 12. 8-bit RDAC (mine) 13. 8-bit rheostat (mine, based on the RDAC) 14. Sample-and-hold for an ADC (mine) 15. Comparator for an ADC (mine) I have not yet written up the list of digital control signals and how they drive each circuit, like I did for the first test chip, but I will do that shortly and push it to the repository README file. Both the first and second test chips need test plans, which will be forthcoming (eventually). The repositories for the two test chips are: 1. https://github.com/RTimothyEdwards/chipalooza_projects_1 2. https://github.com/RTimothyEdwards/chipalooza_projects_2 Both repositories are in the form of a

caravel_user_project_analog

template for the Caravan chip.