#209 [bug] ifnone state-dependent path delay Issue created by likeamahoney Hi, All! I found that

ifnone

condition used here and here is illegal due to SystemVerilog LRM IEEE 1800-2017 and it's previous versions due to section 30.4.4.4 - The ifnone condition description:

The ifnone keyword is used to specify a default state-dependent path delay when all other conditions for

the path are false. The ifnone condition shall specify the same module path source and destination as the

state-dependent module paths. The following rules apply to module paths specified with the ifnone

condition:

—

Only simple module paths may be described with an ifnone condition.

—The state-dependent paths that correspond to the ifnone path may be either simple module paths or

edge-sensitive paths

—If there are no corresponding state-dependent module paths to the ifnone module path, then the

ifnone module path shall be treated the same as an unconditional simple module path.

—

It is illegal to specify both an ifnone condition for a module path and an unconditional simple

module path for the same module path.

Which means that edge-sensitive path can't be specified under

ifnone

condition. Edge sensitive paths can be specified only in

if

conditions which correspond to

ifnone

. IHP-GmbH/IHP-Open-PDK