But I'm working on an implant ROM compiler, so sometime there is diffusion, something there is not, and I'm trying to estimate what range of capacitance I can expect for the word line, trying to use the google docs with parasitics data.

Answering my own question, after re-reading parts of Weste/Harris, I think the poly is flat, it's the underlying substrate that was etched during the STI process which leads to thicker oxide between field poly and substrate vs the gate poly one.

I'm looking at the google docs with the parasitics and the fringe capacitance look quite significant. Am I correct that if you have a wire (so much longer than wide), you need to count twice the length when applying the fringe capacitance numbers ? In which case the fringe capacitance is like 10 times larger than the parallel plate capacitance ... (for a 0.15u field poly).