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Hi. Does openlane use systemverilog
# openlane
m
Hi. Does openlane use systemverilog
v
yes. But limitation coming from Yosys synthesis tools. Refer yosys documentation, which are not supported SV features.
d
OpenLane 2 supports the Synlig SystemVerilog frontend for Yosys if you set 
USE_SYNLIG
to 
true
. However, it is less battle-tested than the Yosys Verilog frontend.
a
You can also request a version of Yosys with Verific as the frontend that works very well. It’s called TabbyCAD and you can request it from YosysHQ on their website
m
Where do you set the synlig to be true?
d
In your design's 
config.json
.
m
I did that
IMG_20241021_121019.jpg
Like this
d
yes
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