Hello, I would like to know how to connect a DAC in Xschem with a SAR in Verilog.

@Carolina Vieira Are you interested in LVS or simulation? Simulation requires a mixed signal capable simulator (unless you can get openroad to output a cdl netlist that you could splice into xschem). For LVS, calling a verilog module from xschem is relatively simple. 1. Create a symbol of your verilog block with all the pins (including power). 2. Set the

type=primitive

property on the symbol 3. Make sure the pins are in the same order as the verilog module. (You can add a

pinnumber

property to each pin, but I find it easier to open the

sym

text file and rearrange the order.) Calling a spice subcircuit from verilog, is trivial. All the standard cells are instances of this. https://open-source-silicon.slack.com/archives/C016HUV935L/p1712918622170979?thread_ts=1712915355.738759&cid=C016HUV935L

I would like to do just one simulation, connecting xschem with SAR in verilog. Can you help me?

I can help with LVS. I haven’t done any mixed signal simulations.

In

$PDK_ROOT/$PDK/libs.tech/xschem/xschem_verilog_import

you can find some scripts to take the output verilog netlist from openroad and make it into a schematic / symbol for xschem together with some examples