Hey all! I'm a student at Stanford, and after toying around with FPGAs and chips for the last few years, I really wanted a tool that made IP reuse as easy as pip install. I built a Verilog Package Manager that does this. You can "vpm include" a top level module, and it auto-includes all the submodules, generates .vh headers, handles synthesis collateral, etc. Here's the GitHub link: https://github.com/getinstachip/vpm/ I'm sending this out to people that might benefit in hopes of receiving feedback. I'd really appreciate it if you could try it out—your suggestions will be included within a few hours :)