Here are the spice files for the schematic and layout respectively.

@Nahum Yonas When extracting the layout using magic, try using these commands

extract no all ;# clear all flags
extract do aliases
extract do local
extract unique
extract

ext2spice lvs
ext2spice short resistor ;# keep both ports but connect them with a 0 ohm resistor
ext2spice -o Flippy_layout.spice Flippy_layout.ext

Make sure your layout has ports defined.

Thank you for your response. However, I am still receiving the same errors.

Your extracted netlist should have a top level

.subckt

with ports and should no longer have parasitic capacitors.

My netlist now has the .subckt with the ports. For some reason my data port is not being recognized. But, I am still getting the property errors.

Can you share the

Flippy_layout.spice

file? Normally, when I run LVS, I use the following format.

netgen lvs "layout.spice layout_top" "schematic.spice schematic_top" setup_file

It might be wise to explicitly state what cell you want to compare (the

"netlist cellname"

format allows this).

Flippy_layout.spice

@Nahum Yonas Before you create your schematic netlist, be sure to set

Simulation -> LVS -> LVS netlist: Top level is a .subckt

. This should create a netlist with a top

.subckt

definition. And then can you try

netgen lvs "Flippy_layout.spice Flippy_layout" "Flippy.spice Flippy" $PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl

Ok, I have tried this and now I am getting a different Final result with the same property errors

Contents of circuit 1:  Circuit: 'Flippy.spice'
Circuit Flippy.spice contains 30 device instances.
  Class: sky130_fd_pr__nfet_01v8 instances:  15
  Class: sky130_fd_pr__pfet_01v8 instances:  15
Circuit contains 18 nets.
Contents of circuit 2:  Circuit: 'Flippy_layout'
Circuit Flippy_layout contains 30 device instances.
  Class: sky130_fd_pr__nfet_01v8 instances:  15
  Class: sky130_fd_pr__pfet_01v8 instances:  15
Circuit contains 18 nets, and 3 disconnected pins.

Circuit 1 contains 30 devices, Circuit 2 contains 30 devices.
Circuit 1 contains 18 nets,    Circuit 2 contains 18 nets.


Final result:
Top level cell failed pin matching.

Logging to file "comp.out" disabled
LVS Done.

It seems the issue has something to do with pin matching/ports in my layout. I will attach my comp.out file. It appears the actual errors are in comp.out around lines 32-43

@Nahum Yonas Looks like you’re making progress! 1. Although you can put the schematic netlist first (schematic-versus-layout), openlane follows the LVS format (layout-versus-schematic). In order to avoid confusion and having to repeat your lvs command every time you ask a question, I suggest you put the layout first in the lvs command. 2. It appears that the schematic netlist does not have ports. Check that you have set

Simulation -> LVS -> LVS netlist: Top level is a .subckt

before generating the schematic netlist from xschem. 3. From the extracted netlist,

clock

,

r

, and

q

are not connected to anything. Please check that you have all the relevant vias and contacts.