What is the meaning of terminal B? Can anyone explain the behavior of this circuit?

Bulk connection. It is part of the cell construction. I assume because it is made out of poly-silicon so there are next order modelling interactions to take into account with simulation depending on what the B pin is connected to. For example it could be in its own isolated well, or connected to the PDN 0V or -3.141V (an arbitrary potential to illustrate this point) Take a look at the standard p-cell generated layers for this device to understand how this is an intrinsic part of the device construction.

Terminal B is the "bottom side" of the resistor. This B terminal allows for the resistor model to include bottom side parasitic capacitors. In the resistor models, this parasitic capacitors are connected between the middle of the resistor and the B terminal. The B terminal allows the circuit designer to control the connection of the parasitic capacitor to minimize the effects of the signals being coupled into the resistor path by this parasitic capacitor. You can think of the B terminal as a electro-static shield to the bottom side of the resistor. If I layout my resistor over the substrate, I connect the B terminal to Ground. If I layout my resistor over a Nwell that is connected to VDD, then I connect the B terminal to VDD.

Can this resistor be isolated? If so, what is terminal B connected to?

Is the 'Bottom Side' also known as the 'substrate' also known as the 'bulk' which has next order (i.e. not directly about resistance) simulation modelling interactions, such as capacitance for which the MetalOxide layer is the dielectric.

Ok now can you isolate the resistor?

I am not sure what you mean by isolate. The parasitic 'bottom side" capacitors are always there. The "B Terminal" to the resistor symbol, always you to control where these "bottom side" capacitors are connected to.

By isolate i mean keep the resistor separate from the substrate, VDD and GND?

Yes, you can put these resistors over an Nwell, where the Nwell is connected to another circuit node that is not VDD or GND.

Can you make Pwell versions, maybe there is an option in the p-cell (parameterized cell) generation in magic to do this as I recall the default is based on top of Nwell

Hi Darryl, my project has not yet started layout, so I don't know what constraints the CAD tools place on the p-cell generation of Poly resistors. From a semiconductor processing stand point, there is no limitation on Poly Resistor being placed on top of Nwell or being placed on top of Pwell. If the CAD tool doesn't allow Poly Resistors over Pwell, then I would loudly complain to Efabless and Skywater.