open-source-silicon.dev

1.PNG

Hi <@U017X0NM2E7>
I wanted to run verilog code of a 2x1 Multiplexer in the openlane2 colab notebook. I'm getting an error in the PDN part of the code. I have attached a screenshot of the error. One solution online for a similar case is: "this design is so trivial that I expect the area isn't big enough to put a power grid. You could switch to a fixed area floorplan or use a very low utilization to increase the area."
How do I implement that in the colab file?

Colab file link:
<https://colab.research.google.com/drive/12r1cJfQLFWe6Jw0xl6Y3PTw3tKa9S7RE?usp=sharing>

<@U07E00P8VQQ> Can you try adding the die size to this step?
```from openlane.config import Config

Config.interactive(
    "spm",
    PDK="sky130A",
    CLOCK_PORT="clk",
    CLOCK_NET="clk",
    CLOCK_PERIOD=10,
    PRIMARY_GDSII_STREAMOUT_TOOL="klayout",
)```

from openlane.config import Config

Config.interactive(
    "spm",
    PDK="sky130A",
    CLOCK_PORT="clk",
    CLOCK_NET="clk",
    CLOCK_PERIOD=10,
    PRIMARY_GDSII_STREAMOUT_TOOL="klayout",

    FP_SIZING="absolute",
    DIE_AREA= (0, 0, 7000, 7000),

)

<@U017X0NM2E7> No changes are made in the output after adding FP_SIZING and DIE_AREA

<@U07E00P8VQQ> Did you see this message?
```[05:45:56] WARNING  Key 'FP_SIZING' provided is unused by the current flow.                           config.py:402```
And then
```[INFO] Extracting DIE_AREA and CORE_AREA from the floorplan                                                        
[INFO] Floorplanned on a die area of 0.0 0.0 15.785 26.505 (µm).                                                   
[INFO] Floorplanned on a core area of 5.52 10.88 10.12 13.6 (µm).                                                  
Writing metric design__die__bbox: 0.0 0.0 15.785 26.505                                                            
Writing metric design__core__bbox: 5.52 10.88 10.12 13.6                                                           ```
Maybe you need `CORE_AREA` too. Sorry, I don’t have much experience with synthesizing designs. I handle the LVS portion.

<@U017X0NM2E7>  I saw the same error as shared in the picture in my first message. I tried the core area variable as well but no changes in the output. The error comes when the circuit is small. For larger circuits the provided openlane 2 code works very well. Thanks for your response.