Hi everyone, I was using this part of the

synth_preamble.tcl

script from ORFS with Yosys to do flat synthesis while preserving a single module. I was getting the error: `Error: no such module `module_name`` on the

select -module $cell

statement. I tried with a small test case with 2-3 small modules and it worked fine there. The original design I tested it with had modules with parameters. It seems the error only occurs with parameterized Verilog modules I tried preserving non-parameterized modules in the original design and it worked. In completely hierarchical synthesis, parameterized synthesized modules names seem to have some string appended at the end. Is it because of this that the module is not found? Is it possible to mark all variants of the parameterized module to be preserved in the hierarchy? Or alternatively, find the updated name of the module and mark it to be preserved? cc: @mehdi

@Matt Liberty can anyone help?

This question is better asked to yosyshq (eg https://github.com/YosysHQ/yosys/discussions). I expect you could use a wildcard

Thanks, I'll try the wildcard approach. There is a script

synth_hier_report.tcl

in ORFS, how does it handle the names? Is it expected to synthesize hierarchically first?

Yes we synthesize hierarchically and then iterate the modules to see which are large enough that we want to keep them in a second partially-flatten synthesis.

I see, it seems like a good solution for our problem. Thanks!