Is there any limitation to the tape-out chip size? If so, I would like to know it in advance, so that I can plan further please 🙂

This chipathon is about relatively small building blocks, not so much about large chips. The question of area will become relevant only once we know what we collectively want to validate in silicon. If you are thinking of designing something that will hit chip size limits on its own, it is probably out of scope.

Most probably we shall target a shuttle of sky130 or gf180 via efabless caravel. If that is true, then for sky130 the max area we get is 3500(y) um x 3000(x) um =~ 10 sqare mm. If gf180, then its little less than 10sqmm.