open-source-silicon.dev

I note that the readme.md instructions in the efabless/clear repo say to use the SOFA branch of efabless/OpenFPGA_bitstream_generation repo for bitstream generation, but I've noticed that commit referenced for the vtr-verilog-to-routing submodule in that branch is currently bogus (e7406bc). Are you all maybe using the commit from the main branch (90ee6e6) instead or perhaps using something else?

So i'm guessing maybe everyone so far is using the binaries baked into the SOFA tree to generate bitstreams <https://github.com/efabless/OpenFPGA_bitstream_generation/tree/SOFA/build/yosys/bin>