#54 KLayout: PMOS and NMOS have different GatPoly Layers Issue created by vkrahul77 In the "IHP Pycells", For Gate The PMOS has "GatPloy.lbl" while NMOS has "Gatpoly.drw" as shown: GatePloy_PMOS_NMOS Also, I've noticed a discrepancy in dimension input between NMOS and PMOS transistors within the tool. Specifically, while "1u" notation is accepted for PMOS, it's not permitted for NMOS. Instead, we're required to use scientific notation such as "1e-6". IHP-GmbH/IHP-Open-PDK