Hi everyone, I'm having the following error when executing the "insert_tiecells" command in openroad: % insert_tiecells "sky130_fd_sc_hd__conb_1/LO" Stack trace: 0# 0x0000000001039206 in openroad 1# 0x00007F6A9C5CE400 in /lib64/libc.so.6 2# ifp:InitFloorplan:insertTiecells(odb::dbMTerm*, std::string const&) in openroad 3# 0x000000000103DA38 in openroad 4# 0x00007F6A9F35CEB2 in /lib64/libtcl8.5.so 5# 0x00007F6A9F3A136C in /lib64/libtcl8.5.so 6# TclObjInterpProcCore in /lib64/libtcl8.5.so 7# 0x00007F6A9F35CEB2 in /lib64/libtcl8.5.so 8# 0x00007F6A9F3A136C in /lib64/libtcl8.5.so 9# 0x00007F6A9F3A9647 in /lib64/libtcl8.5.so 10# TclEvalObjEx in /lib64/libtcl8.5.so 11# Tcl_RecordAndEvalObj in /lib64/libtcl8.5.so 12# Tcl_Main in /lib64/libtcl8.5.so 13# main in openroad 14# __libc_start_main in /lib64/libc.so.6 15# 0x0000000001035DD7 in openroad openroad -version v2.0-4485-g43ab25a

Could you try with a newer version of OpenROAD or submit a GitHub issue with a reproducible testcase?

Hi Vitor, Thank you for your response. Now I have tried with the last version (v2.0-4632-g4a99e88) and I had the same issue. It's quite easy to reproduce. I have made my own design environment and there, I execute each PnR step with the possibility to debug each of it using the -gui option. On each step, I read the db file from the last executed step. I thought that the db file contained all the loaded files (example: lefs, libs, verilog, etc), but then I realize that the insert_tiecells "sky130_fd_sc_hd__conb_1/LO" command only worked if I reload the lib files, and I got the posted error if I just read the db file and then executed that command. Thank you again. Regards,

the odb doesn't include liberty or sdc files as those are read directly by the timer and not the database

Just to double check, if you load the lib files the command works without issue?

Hi Vitor, Exactly. If you load the lib files it works Ok. So, if I understand well, every time you load an odb file, it is better to reload the lib, the lef, the track definitions, everything ? What is included (recorded) inside the odb file ? Only the position, orientation, etc of every instance of the design? Thank you in advance. Best Regards, Rodrigo Iga

the lef & def contents are in the .odb. You only need to reload lib/sdc/spef

Thank you Matt for your response. And the verilog netlist, the floorplan (core and die area definition), the track definitions, etc, are they included in the odb file ? Best Regards,