Last time I tried it, the answer was no. Verilator (as of the last time I tried it) didn't support Verilog primitives and Caravel SoC hand instantiates physical cells (which is a bit annoying and ties itself to one technology node) that makes it hard to simulate more universally.
Linen is a search-engine friendly community platform. We offer integrations with existing Slack/Discord communities and make those conversations Google-searchable.
