Out of curiosity how good are the open source tools at like mosfet level synthesis?

What is MOSFET-level synthesis?

Well like are there tools capable of optimizing how many mosfets are needed for a given circuit?

If you are talking about the digital design synthesis, then AFAIK it has nothing to do with the transistors (directly). What a synthesizer (e.g. Yosys) do is using Boolean Algebra to optimize your RTL code and using less logic gates (so less MOSFETs). Floorplanning is related to back-end process and AFAIK it doesn’t optimize the gates.

Right I know floorplanning doesn't optimize the gates, I just also wanted to know how good it was.

Please note the following quote from the OpenROAD project:

The IDEA program targets no-human-in-loop (NHIL) design, with 24-hour turnaround time and zero loss of power-performance-area (PPA) design quality.

This might help you a lot to have a better understanding about OpenROAD target and the difference b/w this tool and something like ICC II. For more info check this out.

Thanks

No problem. Hope this would help.

I'm just reading Harris and Weste and they talk about transistor level optimization, so I was curious how good the open source solutions were if they existed

Would you mind point me to some references which describe the definition of transistor level optimizations? Are you talking about PPA optimization?

Like how you could make an adder using only Nand gates, but it's more efficient to not do that, similarly you can directly think about it on the transistor level.

IMHO this is a PPA (Power, Performance, Area) optimization question… As I said before, the main objective of the OpenROAD project is to let one person to do the whole back-end process in less than 24 hours. As a result unlike commercial tools (like ICC) you won’t have a lot of options to fully control the whole process and this will lead to less optimized PPA in comparison with commercial tools. On the other hand, using a commercial tool needs a huge amount of man hours and a lot of experts. This is a kind of trade off. However the OpenROAD team is working on this to achieve the ultimate goal of the project:

no-human-in-loop (NHIL) design, with 24-hour turnaround time and zero loss of power-performance-area (PPA) design quality.

Gotcha, yeah that's fair.

Maybe other people could help you more so still wait for other answers…