Hi everyone I am new to Openlane, when I am trying to run my files I am getting the below error...can anyone help me with it. Below are my sdc and design.v: design.sdc:

create_clock -name clk -period 10.0 [get_ports clk]
set_input_delay -clock clk 2.0 [get_ports in]
set_output_delay -clock clk 2.0 [get_ports out]

design.v

module inverter(input wire in, output wire out);
    assign out = !in;
endmodule

check

linter.log

Hey, I checked the errors in linter.log and corrected them. It got resolved...Thank you!!