#148 UDP and SDF forbids post-synthesis simulation with either Icarus Verilog or Verilator Issue created by MaxenceBouvier Hi, I am trying to simulate a post-synthesis design using either Verilator or icarus verilog (iVerilog) tools. The design has been synthesized with YOSYS simulator and in the end instantiates some sg13g2_dfrbp_1 cells. Unfortunately, the behavioral model of these cells rely on: • User Defined Primitives (UDP) description. • Standard Delay Format (SDF) timing definitions. So, I do not succeed running a simulation for the following reasons: • SDF is not supported by Icarus Verilog. (here) • UDP is not supported by Verilator. (here) What do you recommend as a solution, apart from redefining the behavior of sg13g2_dfrbp_1 as simple D Flip Flops? Thanks for your help. IHP-GmbH/IHP-Open-PDK