Quick question regarding design rules: is there a constraint for maximum metal width?

I have seen references to this in discussion to other PDKs, but never had anything be flagged in the SKY130 PDK for the design I taped out. My widest metal area was ~100um or so.

The grid is aligned to the chip origin, as far as I know. However, in the final version of SkyWater's density rules for sky130, they calculate metal densities over the full chip and only do the stepped window for FOM (diffusion) density. Our pattern generation does not look at the existing density, so it will apply patterns to any empty area. So you can't, for example, cover half of the chip with a solid sheet of metal and expect it to pass with 50% density. There is a stress rule for metal over (I think?) 30um which requires slotting, although I also think SkyWater applies slotting automatically, so the rule isn't checked, as it is always correct by design.

Just out of curiosity, is M5 exempt from that rule? I just looked over my design again and I have a 890x525 metal area on M5 M4 M3 M2. I did not see any slots on the decaped IC. But of course I can only see M5.

I don't remember where the slotting was mentioned, or if I'm just mis-remembering it from other processes.

@Tim Edwards is there any criteria for the slotting? That might be of relevance for RF layouts (ground planes, for example, or wide CPW strips). Should I create some kind of "ground dummy" to force a known slotting where the layout would be most sensitive towards unwanted slotting?

@Tim Edwards I was considering sending my IC to be decapped: https://siliconpr0n.org/archive/doku.php?id=mcmaster:start#commissioning . He could also strip M5 and check if M4 or deeper layers are slotted. Would this be interesting / worth it? Or is it just something that skywater would need to be bugged about more?

@Weston Braun: I could just ask the SkyWater engineering team, but a photomicrograph would be definitive. . .