@Kamta Kesharwani I don't know how much aging effects matter on a 150nm cmos process, usually these effects are considerable on nanoscale devices (40nm gate length or lower). http://people.ece.umn.edu/users/sachin/conf/vlsidat13.pdf

Total newb here, how is aging compensated for in these nanoscale devices?

@Zachary Curtis usually aging effects can be compensated by: 1. Design margin: degraded and aged device is still good enough to guarantee circuit functionality after expected lifetime. 2. Avoiding dangerous operating zones for the device, this can be done by adding a cascode device that limits the drain voltage, or by avoiding slow on-off/ off-on transitions or by reducing drain capacitances. 3. Using longer / bigger /parallel devices so current density / electric fields are reduced. 4. Sleep modes to power off analog blocks when not needed. Experts in the matter may have other design techniques to mitigate the problem.

@Stefan Schippers do you believe it's possible for one person to do asic designs at that level?

@Zachary Curtis an Asic design consists of a circuit description, either coded with a HDL language (Verilog, VHDL) or with schematics or both. This circuit must then be translated to a layout, which describes all the layers/masks that are needed in lithography to pattern tre transistors on silicon. Layout generation can either be automatic (the digital HDL to RTL to GDS flow) or manuall (layout of analog blocks). Then the layout must be checked to be equivalent to the source circuit (the so called LVS, Layout vs Schematic) and to comply to the process design rules (the DRC, Design Rule check). Many additional checks are needed, like density checks, Design for Manifacturability checks (DFM), Antenna checks and many more. When layout is finalized optical masks are generated to pattern the structures on silicon. A whole team of process engineers takes care of this at the fab. The skywater 130 pdk allows a single (skilled) person to design a microchip and embed this chip into a framework that provides I/O pads and control logic so that the chip once manifactured can be tested with signal generators / oscilloscopes / Microcontrollers. If the design conforms to all the design rules there is a good chance that the chip will be functional when coming out of the fab.