<@U03DNPRUBFD> i added a .options ITL4=1000 to force more iterations before giving up and simulation...

Stefan Schippers

08/04/2022, 8:00 AM

@Faedra Webers i added a .options ITL4=1000 to force more iterations before giving up and simulation went fine. Attached the changed

DAC_works_not_schematic.sch

with body terminals set to vdd/GND (but this might not be the solution of the convergence issue) and graphs inserted in the schematic.

DAC_works_not_schematic.sch

👍 1

Faedra Webers

08/04/2022, 8:10 AM

awesome! I try it instantly!

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