Hi all, I am having trouble with the MPW precheck for the user_analog_project. This is the output of my log on efabless.com:

[08/02/22 18:27:37 PDT] FAILURE
1 Check(s) Failed: ['Consistency'] !!!






[08/02/22 18:27:37 PDT] FAILED
STDOUT: Loading Job # bbd98af2-dc91-4e3d-9eee-3e64aab5f170 ...
STDOUT: Open Source Shuttle MPW Precheck | Starting Job # bbd98af2-dc91-4e3d-9eee-3e64aab5f170 ...
STDOUT: {{Project Git Info}} Repository: <https://gitlab.com/carllb52/mixed-signal-reram-mpw7-2.git> | Branch: main | Commit: 0c57b1bcff189728d081673a6982bd2f3bd13f41
STDOUT: {{EXTRACTING FILES}} Extracting compressed files in: mixed_signal_circuits-jun13
STDOUT: {{Project Type Info}} analog
STDOUT: {{Project GDS Info}} user_analog_project_wrapper: 94b6ca623f863196471e194445b4875966ebd3c2
STDOUT: {{Tools Info}} KLayout: v0.27.10 | Magic: v8.3.315
STDOUT: {{PDKs Info}} PDK: sky130B | Open PDKs: 05af1d05227419f0955cd98610351f4680575b95 | Skywater PDK: c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
STDOUT: {{START}} Precheck Started, the full log 'precheck.log' will be located in 'mixed_signal_circuits-jun13/jobs/mpw_precheck/bbd98af2-dc91-4e3d-9eee-3e64aab5f170/logs'
STDOUT: {{PRECHECK SEQUENCE}} Precheck will run the following checks: [License, Makefile, Default, Documentation, Consistency, XOR, Magic DRC, Klayout FEOL, Klayout BEOL, Klayout Offgrid, Klayout Metal Minimum Clear Area Density, Klayout Pin Label Purposes Overlapping Drawing, Klayout ZeroArea]
STDOUT: {{STEP UPDATE}} Executing Check 1 of 13: License
STDOUT: An approved LICENSE (Apache-2.0) was found in mixed_signal_circuits-jun13.
STDOUT: {{MAIN LICENSE CHECK PASSED}} An approved LICENSE was found in project root.
STDOUT: An approved LICENSE (Apache-2.0) was found in mixed_signal_circuits-jun13.
STDOUT: {{SUBMODULES LICENSE CHECK PASSED}} No prohibited LICENSE file(s) was found in project submodules
STDOUT: SPDX COMPLIANCE SYMLINK FILE NOT FOUND in mixed_signal_circuits-jun13/openlane/Makefile
STDOUT: {{SPDX COMPLIANCE CHECK FAILED}} Found 55 non-compliant file(s) with the SPDX Standard.
STDOUT: SPDX COMPLIANCE: NON-COMPLIANT FILE(S) PREVIEW: ['mixed_signal_circuits-jun13/Makefile', 'mixed_signal_circuits-jun13/docs/Makefile', 'mixed_signal_circuits-jun13/docs/environment.yml', 'mixed_signal_circuits-jun13/docs/source/conf.py', 'mixed_signal_circuits-jun13/docs/source/index.rst', 'mixed_signal_circuits-jun13/netgen/run_lvs_por.sh', 'mixed_signal_circuits-jun13/netgen/run_lvs_wrapper_verilog.sh', 'mixed_signal_circuits-jun13/netgen/run_lvs_wrapper_xschem.sh', 'mixed_signal_circuits-jun13/netgen/sky130B_setup.tcl', 'mixed_signal_circuits-jun13/verilog/dv/Makefile', 'mixed_signal_circuits-jun13/verilog/dv/mprj_por/Makefile', 'mixed_signal_circuits-jun13/verilog/dv/mprj_por/mprj_por.c', 'mixed_signal_circuits-jun13/verilog/dv/mprj_por/mprj_por_tb.v', 'mixed_signal_circuits-jun13/verilog/rtl/example_por.v', 'mixed_signal_circuits-jun13/verilog/rtl/uprj_analog_netlists.v']
STDOUT: For the full SPDX compliance report check: mixed_signal_circuits-jun13/jobs/mpw_precheck/bbd98af2-dc91-4e3d-9eee-3e64aab5f170/logs/spdx_compliance_report.log
STDOUT: {{STEP UPDATE}} Executing Check 2 of 13: Makefile
STDOUT: {{MAKEFILE CHECK PASSED}} Makefile valid.
STDOUT: {{STEP UPDATE}} Executing Check 3 of 13: Default
STDOUT: {{README DEFAULT CHECK PASSED}} Project 'README.md' was modified and is not identical to the default 'README.md'
STDOUT: {{CONTENT DEFAULT CHECK PASSED}} Project 'gds' was modified and is not identical to the default 'gds'
STDOUT: {{STEP UPDATE}} Executing Check 4 of 13: Documentation
STDOUT: {{DOCUMENTATION CHECK PASSED}} Project documentation is appropriate.
STDOUT: {{STEP UPDATE}} Executing Check 5 of 13: Consistency
STDOUT: HIERARCHY CHECK PASSED: Module user_analog_project_wrapper is instantiated in caravan.
STDOUT: COMPLEXITY CHECK PASSED: Netlist caravan contains at least 8 instances (68 instances).
STDOUT: MODELING CHECK PASSED: Netlist caravan is structural.
STDOUT: SUBMODULE HOOKS CHECK FAILED: The user power port vccd1 is not connected to the correct power domain in the top level netlist. It is connected to mprj/vccd1 but it should be connected to vccd1_core.
STDOUT: {{NETLIST CONSISTENCY CHECK FAILED}} caravan netlist failed 1 consistency check(s): ['SUBMODULE HOOKS'].
STDOUT: PORTS CHECK PASSED: Netlist user_analog_project_wrapper ports match the golden wrapper ports
STDOUT: COMPLEXITY CHECK PASSED: Netlist user_analog_project_wrapper contains at least 1 instances (6 instances).
STDOUT: MODELING CHECK PASSED: Netlist user_analog_project_wrapper is structural.
STDOUT: LAYOUT CHECK PASSED: The GDS layout for user_analog_project_wrapper matches the provided structural netlist.
STDOUT: {{NETLIST CONSISTENCY CHECK PASSED}} user_analog_project_wrapper netlist passed all consistency checks.
STDOUT: {{CONSISTENCY CHECK FAILED}} The user netlist and the top netlist are not valid.
STDOUT: {{STEP UPDATE}} Executing Check 6 of 13: XOR
STDOUT: {{XOR CHECK UPDATE}} Total XOR differences: 0, for more details view mixed_signal_circuits-jun13/jobs/mpw_precheck/bbd98af2-dc91-4e3d-9eee-3e64aab5f170/outputs/user_analog_project_wrapper.xor.gds
STDOUT: {{XOR CHECK PASSED}} The GDS file has no XOR violations.
STDOUT: {{STEP UPDATE}} Executing Check 7 of 13: Magic DRC
STDOUT: Found 0 violations
STDOUT: 0 DRC violations
STDOUT: {{MAGIC DRC CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 8 of 13: Klayout FEOL
STDOUT: No DRC Violations found
STDOUT: {{Klayout FEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 9 of 13: Klayout BEOL
STDOUT: No DRC Violations found
STDOUT: {{Klayout BEOL CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 10 of 13: Klayout Offgrid
STDOUT: No DRC Violations found
STDOUT: {{Klayout Offgrid CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 11 of 13: Klayout Metal Minimum Clear Area Density
STDOUT: No DRC Violations found
STDOUT: {{Klayout Metal Minimum Clear Area Density CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 12 of 13: Klayout Pin Label Purposes Overlapping Drawing
STDOUT: No DRC Violations found
STDOUT: {{Klayout Pin Label Purposes Overlapping Drawing CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{STEP UPDATE}} Executing Check 13 of 13: Klayout ZeroArea
STDOUT: No DRC Violations found
STDOUT: {{Klayout ZeroArea CHECK PASSED}} The GDS file, user_analog_project_wrapper.gds, has no DRC violations.
STDOUT: {{FINISH}} Executing Finished, the full log 'precheck.log' can be found in 'mixed_signal_circuits-jun13/jobs/mpw_precheck/bbd98af2-dc91-4e3d-9eee-3e64aab5f170/logs'
STDOUT: {{FAILURE}} 1 Check(s) Failed: ['Consistency'] !!!

I am stuck at:

STDOUT: SUBMODULE HOOKS CHECK FAILED: The user power port vccd1 is not connected to the correct power domain in the top level netlist. It is connected to mprj/vccd1 but it should be connected to vccd1_core.
STDOUT: {{NETLIST CONSISTENCY CHECK FAILED}} caravan netlist failed 1 consistency check(s): ['SUBMODULE HOOKS'].

I belive there is currently a issue on the caravel repo: https://github.com/efabless/caravel/issues/105 If Anyone has any suggestions that would be greatly appreciated.