module test; wire qq; reg ck, dd, ss; sky130_fd_sc_hd__dfstp_2 1836 ( .CLK(ck), .D(dd), .Q(qq), .SET_B(ss) ); always #5 ck = ~ck; initial begin $monitor($time," TEST DISPLAY = %b %b %b %b", ck, dd, qq, ss); ck = 0; dd = 0; ss = 0; #20 ss = 1; #100 $finish; end endmodule ~ The above is a small test case using a dff cell from sky130 fd_sc_hd. Compiled as follows: iverilog test.v ./dependencies/pdks/sky130B/libs.ref/sky130_fd_sc_hd/verilog/*.v. The simulation result shows that the output q is always x. How to resolve this? @DESKTOP-6TA75K4:~/projects/rtl_efab$> ./a.out ck d q ss 0 TEST DISPLAY = 0 0 x 0 5 TEST DISPLAY = 1 0 x 0 10 TEST DISPLAY = 0 0 x 0 15 TEST DISPLAY = 1 0 x 0 20 TEST DISPLAY = 0 0 x 1 25 TEST DISPLAY = 1 0 x 1 30 TEST DISPLAY = 0 0 x 1 35 TEST DISPLAY = 1 0 x 1 40 TEST DISPLAY = 0 0 x 1 45 TEST DISPLAY = 1 0 x 1 50 TEST DISPLAY = 0 0 x 1 55 TEST DISPLAY = 1 0 x 1 60 TEST DISPLAY = 0 0 x 1 65 TEST DISPLAY = 1 0 x 1 70 TEST DISPLAY = 0 0 x 1 75 TEST DISPLAY = 1 0 x 1 80 TEST DISPLAY = 0 0 x 1 85 TEST DISPLAY = 1 0 x 1 90 TEST DISPLAY = 0 0 x 1 95 TEST DISPLAY = 1 0 x 1 100 TEST DISPLAY = 0 0 x 1 105 TEST DISPLAY = 1 0 x 1 110 TEST DISPLAY = 0 0 x 1 115 TEST DISPLAY = 1 0 x 1 test.v21 $finish called at 120000000000000 (1ps) 120 TEST DISPLAY = 0 0 x 1

i'm a total noob, so forgive me if this is a really stupid answer, but does

qq

need to be connected to something first? you have everything else connected to a known value, but how could the simulator know what value q would take if it's just a floating output?

In gate level simulation there is no concept of initial value. The flip flops are set or reset to 1/0 by the signal set/reset. In the test case ss is 0 at the beginning. So, the qq should set to 1 first (#0) and remain at 1 till ss goes 1. After ss is de-asserted, qq should follow dd at rise/fall edge of clock.

it looks like these two are used for the implementation: https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd/blob/ac7fb61f06e6470b9[…]c25268f62fbd7b1/cells/dfstp/sky130_fd_sc_hd__dfstp.behavioral.v and https://github.com/google/skywater-pdk-libs-sky130_fd_sc_hd/blob/ac7fb61f06e6470b9[…]models/udp_dff_ps_pp_pg_n/sky130_fd_sc_hd__udp_dff_ps_pp_pg_n.v