I have verified my design at RTL level and I am satisfied. Now I want to verify at gate level. I have replaced the RTL by the gate level netlist from $CARAVEL_ROOT/verilog/gl/<mydesign>.v. I am using stdcells from $PDK_ROOT/sky130B/libs.ref/sky130_fd_sc_hd/verilog/*.v to compile. And I have my own testbench to verify. Is it the right approach? Is it expected to match the RTL level verification results? Do I need to take care or know anything more?
Note that, this is my own verification setup, not the caravel verification targets.
a
Arman Avetisyan
07/29/2022, 7:20 AM
I dont know if this got fixed, there was a bug with the verilog declaring wire 1; which wrong syntax.
+ Other than the simulation being really long you should be good
👍 2
d
donn
07/29/2022, 5:26 PM
Precisely.
l
Lab Lecture
08/02/2022, 7:15 AM
I was trying to compile verilog simulation models of standard cells using icarus verilog (iverilog). If I use -DUNIT_DELAY -DFUNCTIONAL then getting syntax error. Screenshot attached. Can anyone look into it. This is urgent for doing gate level simulation.
If I don't use those defines (-D...) it compiles fine. But the dff output is always x. Input (d) doesn't propagate to output (q) and set/reset even can't change their output.
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