@Stefan Schippers Quick Question: As we start to work on larger and more complex designs in OS tools we are bumping into things we will need automated in the tools. One of the neat tools could take a pin list from a source. (Allowed sources would be symbol, layout, verilog, other tbd) and port those pins to another view (symbol, schematic, verilog, other tbd). This is particularly good for helping to encapsulate an analog design in a top down design flow. The verilog netlist is usually the first thing developed. (Often from HLS or HDL or now from AI). Then the ports can be transferred to schematic and symbol in seconds enabling very rapid symbol development and accelerating schematic development. is there anything like this already in the open source? (Doesn't seem too complex, just don't want to reinvent the wheel if it is already done by somebody.)