@Tim Edwards If I rely only on the precheck consistency checks on the server side, issues like I list below are not caught, as my team found on a recent tapeout which had a digital macro fail in silicon testing (traced back to these layout issues): • flipping power and ground for a digital macro at the wrapper level (e.g. vccd1 of user project wrapper connected to vssd1 of macro) • shorting wrapper level power connection on Metal 4 to an internal digital macro route also on Metal 4 For a mixed (analog+digital) design, where I am using the user analog project wrapper and multiple macros, which LVS checks can I at least be running locally prior to submissions to ensure the full layout is indeed correct, confirming things like: • layout of digital macros are matching the openlane generated powered verilog • layout of analog portions are matching the xschem schematics • power from user project wrapper is connecting to the correct pins of analog and digital macros Looking at the templates here, it seems like I would want some combination of the analog and digital configs, but it's not clear I can capture all levels of LVS checks very easily - this seems like a template that should already exist for anyone doing mixed signal designs, specifically with an analog top-level and digital macros. Should I be generating a top level schematic that includes pasting in the gate level powered verilog from openlane? https://github.com/efabless/caravel_user_project_analog/blob/main/lvs/user_analog_project_wrapper/lvs_config.json

@Jordan Thanks for the feedback. I’m working to improve the open source LVS system including LVS for mixed signal designs. We’ve uncovered many issues and are working to make LVS as painless as possible (at least running LVS - debugging mismatches is still pretty painful). The most recent

caravel_user_project/Makefile

includes the

lvs-<block>

target where

<block>

is a subdirectory of

lvs

and contains an

lvs_config.json

file. (ie.

lvs/<block>/lvs_config.json

). Unfortunately, the

caravel_user_project_analog/Makefile

may not have this target (the analog version of the

Makefile

may be out-of-date). The lvs system using

lvs_config.json

is hierarchical. For example, if you had digital blocks

digital1

and

digital2

each with

lvs_config.json

files, you could include these in your

user_analog_project_wrapper/lvs_config.json

file like this:

"INCLUDE_CONFIGS": [
    "$UPRJ_ROOT/lvs/digital1/lvs_config.json",
    "$UPRJ_ROOT/lvs/digital2/lvs_config.json"
]

And it should pull all the relevant information. There are some things that you need to be careful of: • In xschem, create a symbol for each digital block with the pins in the same order as the verilog port order. You can use the

sim_pinorder

(I think) property to order the pins, but I find it easiest to open the text file and put them in order there. • Set the symbol

type=primitive

property (not

type=subcircuit

). • Mixed signal LVS is case insensitive, so be sure your verilog doesn’t use names that only differ in case. • Analog layouts may require selective flattening during LVS. This can be specified in the

lvs_config.json

file, so you shouldn’t need any preprocessing. I’d be happy to help with any questions.

Thanks for the reply. Are there any outstanding LVS issues you can point me to that I can be aware of or try and fix myself? I will try putting something together with the above guidance - I wanted to get a feel for current status of LVS before I spent time doing anything custom, and it sounds like it’s still being improved in terms of errors and ease of use on your end, but is much improved, and I should be able to make a custom configuration file and likely edit the analog wrapper makefile a touch to get things going.

I’ve been able to run LVS on all the designs that have the necessary components. I don’t think there’s anything missing from the flow. There may still be a few gotchas somewhere though. Things like magic silently (or rather quietly) ignoring devices created through overlap of layers in different hierarchies or netgen matching empty cells to non empty cells.