Hi all, may I know if simple combinational circuits such as half or full adders can go through the ORFS flow? And if so, is the SDC file, the config file and the structural Verilog code sufficient?

In short, yes, we've been able to run simple things like a one-hot to binary encoder through the flow without much problems. Simply mark all inputs as non-clock inputs and it will do its thing. One thing to keep an eye on is that for small circuits you may need to reserve quite some excess chip area, for example by setting the utilization low. Otherwise the PDN won't fit (assuming you're using the default one from the scripts)

Alright thanks!

change module name from 'half_adder' to 'halfAdder'

Got it now, thanks!