@Stefan Schippers I have implemented DRC rules for the symbol library of

ihp-sg13g2

technology. Since each symbol file

.smy

was edited is there any method to update the existing schematics, which use the symbols. Unfortunately File->Reload (Alt+S) does not work as expected.

If you change a symbol, a reload of a schematic that uses that symbol will reload the new symbol as well.

@Stefan Schippers thank you for providing the answer and referencing video however it does not address the issue I have 100%. So, after updating the symbols of our IHP pdk, the model's parameters such as

w

,

l

are now with lower case letters. The File->Reload command does update the symbol however when I try to change the parameters (attributes) I still have it with upper case. There is more, the change of

W

, or `L`does not reflect in the actual .spice netlist. After reviewing the content of the

sch

file I found that the attributes are there and one can edit it manually or by manual replacement of the symbol. The question is if there is other more efficient way to do so.

Yes, the instance attributes are in the schematic. I think the quickest way is to edit the .sch file with a text editor and replace occurrences of W= and L= with lower case w= and l=. attributes are case sensitive, since for Verilog w and W are different things. So an instance attribute W=... does not assign symbol w attribute.

@Stefan Schippers thank you. I will update manually. BTW the DRC rule checks work fine. It will be available in our dev branch soon.

May be for this kind of issues I need to implement a more sophisticated search & replace feature to replace the tokens instead of their values, so: "find all MOS instances with W= and change to w= ...".

@Stefan Schippers

find /path/to/directory -type f -exec sed -i -e 's/W=/w=/g' -e 's/L=/l=/g' {} +

worked for me to update all the schematic files

@Krzysztof Herman Yes i also do something like that in these situations. It works, despite not being very user friendly.