#42 Major bug/problem in the a22oi_1 standard cell Issue created by sergeiandreyev ⚠️ IMPORTANT There is functional inconsistency between physical design/transistor-level schematic and Liberty/Verilog description of the a22oi_1 cell, if the cell is used in the design this will lead to a chip not functioning as expected. Other cells could be affected as well.. Thanks to ETH Zurich team that found this critical issue! IHP-GmbH/IHP-Open-PDK