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Hi, I have designed a 3-stage ring oscillator using CMOS inverters both in LTSpice and Xschem+Ngspic...
# analog-design
k
Hi, I have designed a 3-stage ring oscillator using CMOS inverters both in LTSpice and Xschem+Ngspice, when I measure the frequency of their outputs, the LTspice waveform gives me around 18.89GHz whereas the one designed using Xschem+Ngspice gives me 14.8GHz; I am using the same device sizes, same supply voltage, same time step (ik LTspice has dynamic step size but I have set max to the same as ngspice). I am guessing, such a difference in results is not normal. I am using a free 32nm predictive model file. It should also be noted that there is difference in the max voltage these oscillators are attaining, in ngspice they can reach around 980mV but in LTspice, they are getting to around 945mV
Ring_Osc.sch
Here is the LTspice output for the same:
s
@Koustubh to add even more noise to the discussion I tried Xyce and it gives 21.7GHz ringosc oscillation frequency. Seems each simulator gives its own results.
Ring_Osc.sch
k
@Stefan Schippers I was trying to reproduce the results in this paper by Prof Razavi but, given that the PTM file I'm using is different from what he would have used in the paper, I think XYCE gets the closest to the reported 22.6GHz. But given that LTspice and ngspice are both essentially spice their results shouldn't differ as much as 3-4GHz...
s
@Koustubh I don't know if Xyce really has the most accurate result. From Xyce log I get these warnings:
Copy code
***** Executing netlist /home/schippes/.xschem/simulations/Ring_Osc.spice

***** Reading and parsing netlist...
Netlist warning in file /home/schippes/.xschem/simulations/Ring_Osc.spice at
 or near line 34
 Device model NMOS: Model card specifies BSIM4 version 4.0 which is older than
 the oldest version supported in Xyce (4.6.1).  Using oldest version available.
 
Netlist warning in file /home/schippes/.xschem/simulations/Ring_Osc.spice at
 or near line 102
 Device model PMOS: Model card specifies BSIM4 version 4.0 which is older than
 the oldest version supported in Xyce (4.6.1).  Using oldest version available.
t
What's the predictive model file you are using?
k
@Troy Benjegerdes This is the PTM.
32nm_HP.pm
I just tested with NCSU's freepdk 45nm (VTG models Slow Slow Corner), keeping the same ratios i.e. for 40n/120n --> 45n/135n ; 40n/240n --> 45n/270n ; 40n/1600n --> 45n/1800n and the results still vary from simulator to simulator
I am getting an even wider gap in the frequencies, around 19.68GHz for ngspice+Xschem and around 25GHz for LTspice
@Tim Edwards @Stefan Schippers any idea why this might be happening?
Has it been tested using just BSIM models before? The difference between results from ngspice, XYCE and proprietary tools
s
@Koustubh If there are no differences in the circuit and in the provided models I think the question is for the simulator developers.
k
Are there any simulator developers here?
(on this slack server)
t
@Koustubh: @Eric Keiter (also see #xyce) and @Holger Vogt (but I don't think Dietmar Warning is on this Slack workspace). Also CedarEDA (@Keno Fischer) is another simulator to try, as is gnucap.
k
@Tim Edwards is CedarEDA free and/or Open Source? It seems great.
s
@Koustubh Important update, in my previous simulation result post I was not correctly setting the temperature to 75C for Xyce. After the fix the Xyce sim and ngspice sim are perfectly in accordance
👍 2
g
It is easy to share netlis + lib. And just rerun on any simulator.
Then compare the results
k
I have shared the xschem files at the beginning of the thread, it contains the required library definitions. You can make netlist from it
Hi everybody......so as it turns out, when you copy the netlist generated by LTspice, make the necessary changes and run it with ngspice, the results agree with LTspice's initial results. But even after comparing the two netlists side by side, I could not find any difference between the two which would cause such an error. (except that in the Xschem circuit I haven't made use of any subcircuits but in the LTspice schematic I have made a subckt for the inverters) here are the netlists for comparison. TLDR : I goofed up while drawing the schematic on LTspice, due to the default color scheme it looked like the body of the mosfets was connected but instead actually it was just floating somewhere but I still dunno where, but results agree on both sims if you take the ltspice netlist and run it via ngspice I would like to apologise for having caused all this ruckus; I am new with the foss tools and trying to learn them.
LTspice.spiceXschem.spice
👍 1
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