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Ok, not really `magic` but `netgen` but there isan't a channel for that AFAICT. Is `netgen` supposed...
# magic
t
Ok, not really 
magic
but 
netgen
but there isan't a channel for that AFAICT. Is 
netgen
supposed to support non declared wires in input verilog netlist ? Like in verilog there is a default nettype and so declaring wire isn't required. Is netgen supposed to accept that ? I get confused because it seems to work inside of ports of instances but not in 
assign
.
t
There is an #lvs channel which is split between questions about netgen and klayout.
I guess in theory netgen should support implicitly declared wires. Any problems are more likely to have to do with the assignments themselves. Netgen's verilog parser doesn't try to parse the entire language, just whatever part is considered structural verilog. But assignment statements are partly behavioral and partly structural, and there are a bunch of ways to split and join nets in an assignment. I can't guarantee that netgen captures all the possible ways that assignment statements can be used in verilog. Of course, it could also just be a bug.
m
@tnt do you have a sample case? Most generated verilog gate level netlists I’ve seen, start with the ports, followed by the wire definitions, then the instances, and finally the assign statements. Are you maybe using assign statements to connect a net that isn’t used anywhere but an assign statement?
t
(oops, missed #lvs sorry ...) Here's an example. Error is
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Improper assignment;  right-hand side cannot be parsed.
Left-hand side is "vdda1".
Improper expression is "vapwr".
And the line is just :
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assign vdda1 = vapwr;
If I add 
wire vapwr
then it works.
openframe_project_wrapper.pnl.v
@Mitch Bailey Oh you're right that this net is only used in assign statement ... (several of them, it ends up connecting several pins together).
Is that not supported ?
m
@Tim Edwards?
t
If I swap 
assign vapwr = vdda1;
that also works but unfortunately that's not the way it gets written by OR 😕
I tried making sense of the verilog LRM to know if that was valid but couldn't be sure 😅 But I tried 
iverilog
and it seems to agree with 
netgen
in that only the LHS can be an undefined wire, the RHS should already be existing "some other way".
Although I think there is still a bug in 
netgen
because if I correct the net list by adding 
wire apwr;
declaration it works fine. If I correct it by swapping the assignments 
assign vapwr = vdda1;
it reads it but then fails pin matching.
m
@tnt Are you extracting and comparing using your own scripts or the precheck version?
t
@Mitch Bailey This is the LVS that we run ourselves at the end of the flow.
m
There’s a netlisting directive
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ext2spice short resistor
that may fix the port mismatch (if you’re not using it already).
t
We're already using that.
👍 1
m
And your using a relative new version of netgen?
t
The latest.
I mean, it can't work, I see it in the code, see the issue I opened and related PR.
👍 1
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