I am putting a last effort into getting my design done. I have some questions that I am unable to resolve by myself in the available time. I would be grateful if anybody could give me some pointers, I will also consider this a "public layout revision" to avoid flooding @Tim Edwards with potentially simple questions. The images below are the mixed-signal parts of my circuit: 1) trim0-3 are digital signals, they are used to short parts of a feedback resistor that controls the gain, which lies in the analog domain. 2) There is an enable PMOS, the 'ena' signal is supposed to be in the digital domain, but the "enabled" circuit is in the analog domain. The question: what should I do about deep nwell regions and dvdd/dvss signals? I am guessing: 1) The digital trim transistors should be put directly on the substrate, in that case dvss would not be used. 2) The analog elements should be placed in a deep nwell, the floating p region over the well should be connected to avss. 3) The enable PFET is already inside an N-well, so dvdd would only be used inside my circuit to tie that well to it. (Unfortunately, it is placed on the opposite side of the layout). 4) While drawing, I am using the script to generate the deep n-well for the analog circuit, but I need to cut out a square in it to fit the digital transistors (see the last image). Is that ok? (Re-)Drawing the cutout is a lot of work. The well will unfortunately touch or be very close to the transistors regions, the DRC checker seems to be ok with that. Sorry for the long post, but I think that solving this I will be ready to go.

Well, I'm used to being flooded with questions, simple or not. Your design is all in the 1.8V domain. The idea behind this bandgap is that it has its own 1.8V domain that is generated by the low-power voltage regulator. So that's your 1.8V

avdd

. The digital signals will be in a different 1.8V domain (

vccd1

, say). But there's not any way to couple a signal between those domains other than to drive a buffer on the source side in the

vccd

domain with the digital trim bit, and buffer it again on the destination side with a buffer in the

avdd

domain. So I think you just need to put a deep nwell under your entire circuit block, and make sure you buffer each of the trim bits and the enable bit with an extra buffer at the input to your block.

Good, this makes everything much easier, I will use this weekend to finish this and do LVS.

@Adan Kvitschal: If you put a deep nwell under all of it, then your nwells are already connected through the deep nwell. But yes, it's fine to merge them together.

Ok, thanks Tim. Sometimes I worry about process limitations that I am not aware of and that DRC could 'overlook' for some reason.

I worry all the time about such things and what effect they have on matching, and such questions are nearly pointless to ask because proving them would require making a test chip of a thousand layout variations and carefully measuring each one. I would really like to be able to make definitive statements about those kinds of layout practices.

@Tim Edwards Just a quick help with the MiM capacitor: I am using the standard MiM with 5x5 um, but it creates a contact to M4 that isn't useful for me since I am routing from M1-M2. Should I draw it from scratch to get better results? Also, I heard it had a polarity, but I didn't find solid information about it going through the docs.

(1) The contact goes up to metal 4 because MiM caps are an antenna hazard. Some foundries require that the bottom MiM cap plate be connected up one metal layer. SkyWater doesn't have such a rule, but it's good practice. Of course, you are always free to just draw the cap by hand or edit/copy the generated cell. (2) The MiM cap has "polarity" in the sense that the two plates are not interchangeable: The bottom plate faces the substrate and therefore has much more parasitic cap to everything underneath the MiM cap. By contrast, a metal finger cap (vertical parallel plate or "vpp" caps in the SkyWater cell library) are perfectly symmetric.