hello @Boris Murmann @Amro Tork @Harald Pretl, our student @Daniel Arevalos is finishing an LDO test chip for next week's tapeout, with a lot of help from @Krzysztof Herman. We are concerned about ESD protections in bare pads which go directly to transistor gates - there are no models available in opensource and therefore we can't simulate them. Did you face this issue? A possible option is to place protection but with the option of cutting them with FIB/laser. I proposed two ideas but I'm not completely sure if we could create an issue we are not seeing. The first one is to be able to cut just the protection diodes, the other one to cut the full pad (I attached two doodles of this). We would really appreciate your thoughts on this!

Not sure I understand. Which models are not available? Also, why not use the existing analog pad for esd?

@Boris Murmann maybe I misunderstood, but apparently there are no available models for the analog pads (from @Krzysztof Herman's comment). We could use the entioned analog pad, but there is the uncertainty of the loading effect. That's why we are thinking about possibilities to remove it in case we find issues, or am I being too mistrustful with this?

There is a spice netlist of the analog pad. Just make a symbol and include it in your schematic. That's what I did for our chip.

@Boris Murmann thanks a lot for your help, the output load (e.g. Probe cap) is already there, but were insecure about the pad @Daniel Arevalos let's take a look a this!

@Jorge Marin here goes the structure w can try. I will ask what rules shall we used for FIB in order to cut the connection to the ESD diodes.