@Amro Tork @Farag Elsayed I am testing a simple circuit for LVS purposes and found some issues. The principal inconsistency is that in the KLayout data viewer the ptap1 and ntap1 appears as diodes with respective cathode and anode. In the extracted netlist as resistors (as it should be). Anyway I still can not make a clean LVS. Here are the netlists and the layout.

** sch_path: ../design_data/xschem/cinv.sch
.subckt cinv in1 out1 vdd vss
*.PININFO in1:B out1:B vdd:B vss:B
D1 sub in1 dantenna l=780n w=780n
D2 in1 well dpantenna l=780n w=780n
R3 sub vss ptap1
R4 well vdd ntap1
M3 out1 in1 vss sub sg13_lv_nmos L=0.130u W=0.715u ng=1 m=1
M4 out1 in1 vdd well sg13_lv_pmos L=0.130u W=1.120u ng=1 m=1
.ends
.end

* Extracted by KLayout with SG13G2 LVS runset on : 17/05/2024 14:34

.SUBCKT cinv in1 out1 vss vdd
D$1 \$6 in1 dantenna A=0.6084 P=3.12 m=1
D$2 in1 \$5 dpantenna A=0.6084 P=3.12 m=1
R$3 \$5 vdd ntap1 A=0.6084 P=3.12
R$4 \$6 vss ptap1 A=0.6084 P=3.12
M$5 vss in1 out1 \$6 sg13_lv_nmos L=0.13 W=0.715 AS=0.2431 AD=0.2431 PS=2.11
+ PD=2.11
M$6 vdd in1 out1 \$5 sg13_lv_pmos L=0.13 W=1.12 AS=0.3808 AD=0.3808 PS=2.92
+ PD=2.92
.ENDS cinv

Hi @Krzysztof Herman Regarding the class used for both ptap1 and ntap1 devices, yes it's a diode as it's the closest structure to the layout of these devices, but adapted to function as resistors. Could you plaese share the GDS file used for further investigation? Thank you.

cinv.gds,cinv.spice

@Krzysztof Herman • I found the following: ◦ Used ntap1, ptap1 in the cdl don't have parameters. ▪︎ We compare A, P parameters for both devices, we should pass either the A,P or W,L to be compared. ◦ According to provided cdf, the order of the connection should be ▪︎

TIE

WELL

for ntap1 ▪︎

TIE

SUB

for ptap1 So any of the following cdl will pass

** sch_path: /home/herman/github/KrzysztofHerman/IHP-Open-DesignLib/ts_pr_May2024/design_data/xschem/cinv.sch
.subckt cinv in1 out1 vdd vss
*.PININFO in1:B out1:B vdd:B vss:B
D1 sub in1 dantenna l=780n w=780n
D2 in1 well dpantenna l=780n w=780n
R3 vss sub ptap1 A=0.6084p P=3.12u
R4 vdd well ntap1 A=0.6084p P=3.12u
M3 out1 in1 vss sub sg13_lv_nmos L=0.130u W=0.715u ng=1 m=1
M4 out1 in1 vdd well sg13_lv_pmos L=0.130u W=1.120u ng=1 m=1
.ends
.end

Or

** sch_path: /home/herman/github/KrzysztofHerman/IHP-Open-DesignLib/ts_pr_May2024/design_data/xschem/cinv.sch
.subckt cinv in1 out1 vdd vss
*.PININFO in1:B out1:B vdd:B vss:B
D1 sub in1 dantenna l=780n w=780n
D2 in1 well dpantenna l=780n w=780n
R3 vss sub ptap1 w=0.78u l=0.78u
R4 vdd well ntap1 w=0.78u l=0.78u
M3 out1 in1 vss sub sg13_lv_nmos L=0.130u W=0.715u ng=1 m=1
M4 out1 in1 vdd well sg13_lv_pmos L=0.130u W=1.120u ng=1 m=1
.ends
.end

👍

Please refer to

Parameters Information

section for more info about LVS used parameters for each device. I will update the schematic view parameters after being changed. https://ihp-open-pdk-docs.readthedocs.io/en/latest/lvs/04_09_taps.html#ptap1

Other question. In which part you define that

.text

layer is used to assign pin names on the layout ?

You mean which part in the LVS rule deck?

exactly

great, thank you!

We plan to remove the labels for base layers (poly, activ) since they are no longer used in the latest DRM (agreed in last meeting). Thank you.