Last 7 hours - VLSI Product Development Cycle: From Customer Requirements to SoC Design and Implementation Had an excellent session during the SFAL program with all participants. Here's what we discussed. Registration closes in 7 hours https://www.vlsisystemdesign.com/sfal/ Product Cycle Overview Location A: Customer Requirements and PPA Capabilities • Inputs: ◦ Customer requirements: Need for multiple apps (e.g., YouTube, ChatGPT, LinkedIn) to open within 10ms. ◦ Constraints: Fit within the size of an iPhone, run on a basic battery. ◦ Performance, Power, Area (PPA) capabilities. • Output: Technical details and conversations focused on frequency (100MHz), power consumption, and area constraints. Location AB: Conversion to Technical Details • The requirements are translated into specific technical parameters: ◦ Clock constraints: 0.8ns. ◦ IO delays: 5% of the clock period. ◦ IO slews: Some percentage of the clock period. Location B: Design and Implementation • RTL Design/Architect: Develops the register-transfer level (RTL) architecture. • Synthesis Engineers: Convert the RTL design into a gate-level netlist. • IP Designers: Design specific intellectual property (IP) blocks, such as 8x PLL and 10-bit DAC. • CAD: Uses computer-aided design for layout and optimization. • Physical Designers: Focus on the physical layout of the chip. • SoC Designers: Integrate various IP blocks and design elements into a cohesive system-on-chip (SoC). • Physical Verification: Ensures the physical layout meets design rules and specifications. • Post-Silicon Validation: Validates the chip's performance and functionality after fabrication. Role of SoC Designers • Integration: SoC designers are crucial in integrating various IP blocks and design elements into a single SoC, ensuring seamless functionality. • Design Implementation: They make decisions on which process design kit (PDK) to use and which IPs need to be incorporated. • Constraint Management: They manage design constraints related to power, performance, and area, ensuring the SoC meets required specifications and operates efficiently. Manufacturing Process and Yield • The manufacturing process involves various technology nodes (e.g., 130nm, 180nm) and foundries (e.g., TSMC, Skywater, GF, SCL Chandigarh). • The yield, indicating the percentage of functional chips produced, is targeted at 99%. Summary The product cycle involves translating customer requirements into technical specifications, designing various components, and integrating them into a complete SoC. SoC designers play a pivotal role in integrating different IPs, managing design constraints, and ensuring the overall functionality and performance of the chip. Want to apply for Physical design or SoC design roles? Join the SFAL program in next 7-hours https://www.vlsisystemdesign.com/sfal/