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Hi, I've found that klayout lvs extraction with `run_mode=flat` is adding a lot of ports and shortin...
# ieee-sscs-dc-23
a
Hi, I've found that klayout lvs extraction with 
run_mode=flat
is adding a lot of ports and shorting mim-cap inputs. All our design is LVS clean with 
deep
run mode, but not with 
flat
.
Copy code
... run_mode=deep
R1  cap_in  diff_vout  vss 10000 ppolyf_u_1k L=10U W=1U
C1  cap_in  vout       9.68e-13 cap_mim_2f0_m4m5_noshield A=484P P=88U

... run_mode=flat
R1  vout  diff_vout    vss 10000 ppolyf_u_1k L=10U W=1U
C1  vout  vout         9.68e-13 cap_mim_2f0_m4m5_noshield A=484P P=88U
This is the command:
Copy code
python $PDK_ROOT/gf180mcuD/libs.tech/klayout/lvs/run_lvs.py \
    --variant=D \
    --run_mode=flat \
    --thr=8 \
    --lvs_sub=vss \
    --run_dir=... \
    --layout=ota.gds \
    --netlist=ota_noprefix.spice \
    --topcell=ota \
    --combine \
    --schematic_simplify \
    --net_only \
    --top_lvl_pins \
    --purge \
    --purge_nets
@Amro Tork @Juan Sebastian Moya @Tim Edwards @Mitch Bailey I've resumed the procedure to get the same problem in this project. • 
make
will generate the 2 lvs reports and netlists. • 
make klayout-lvs-view
will show only the reports • The specific problem can be seen then comparing the netlists, 
ota_not_flattened.cir
is correct, 
ota_flattened.cir
connects capacitor ports. Both are formatted to simplify comparison.
lvs-flat-problem.zip
a
@aquiles viza Do you have text down the hierarchy in your design?
a
That's exactly the problem, there's a 
vout
on a subcell. Thanks Amro.
a
That's the problem
If you want to run flat, you have to remove all text from sub cells only only keep the top one.
Commercial tools does that automatically, I remember we have made some changes in the code to do that internally as well at some point.
But I believe it was not part of the release.
My recommendation for LVS, do not run flat unless it's mandatory.
Use deep all the time.
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